1. Field of the Invention
The present invention relates to an apparatus and a method for composing a cache memory of a wireless terminal having a coprocessor. More particularly, the present invention relates to an apparatus and a method capable of reducing the number of additional memory devices in a wireless terminal by enabling a coprocessor to have a cache function.
2. Description of the Related Art
In a system having a main processor and a coprocessor, the main processor controls the general operation of the system and the coprocessor controls a specific function under the control of the main processor. Such a structure is currently being employed in wireless terminals performing complex functions. For example, in a wireless terminal processing an image signal, the main processor of the wireless terminal controls the communication and the general operation of the wireless terminal and the coprocessor thereof processes signals for performing a specific function under the control of the main processor. A wireless terminal having a coprocessor as described above may include a wireless terminal having a camera, a Personal Digital Assistant (PDA), or a wireless terminal providing a Video On Demand (VOD) function.
A system having a main processor and a coprocessor as described above may have a structure as shown in FIG. 1. Hereinafter, a description will be given on an assumption that the system is a wireless terminal and the coprocessor is a multimedia coprocessor for exclusively processing an image signal.
Referring to FIG. 1, a main processor 100 controls the communication and the general operation of the wireless terminal. A first flash memory 110 stores a boot and loader program, main operation programs, and a flash file system of the main processor 100. A second flash memory 120 is a non-volatile memory (NVM) for storing data, such as contents data, font data, bit map data, or phonebook data, which requires a permanent storage. A random access memory (hereinafter, referred to as a RAM) 130 may be used as a work memory of the main processor 100. An additional peripheral device 140 represents devices operating under the control of the main processor 100. Herein, the additional peripheral device 140 may include a keypad, a display unit, a wireless communication unit, a communication unit, and the like.
A coprocessor 200 exclusively processes a specific function under the control of the main processor 100. Herein, it is assumed that the coprocessor 200 processes multimedia data. A first flash memory 210 stores a boot and loader program, main operation programs, and a flash file system of the coprocessor 200. A second flash memory 220 stores data (such as, contents data), which require a non-volatility, according to the function of the coprocessor 200. A RAM 230 may be used as a work memory of the coprocessor 200. When the coprocessor 200 is a processor exclusively performing an image processing, a display unit 240 displays an image signal processed under the control of the coprocessor 200. Herein, when only one display unit 240 exists in the wireless terminal, the display unit 240 may become a peripheral device accessed by the main processor 100 and the coprocessor 200. An additional peripheral device 250 represents devices operating under the control of the coprocessor 200. Herein, when the wireless terminal is a camcorder, the additional peripheral device 250 may include a MultiMedia Card (MMC) I/F module, a camera, etc. Further, contents data stored in the second flash memory 220 may become image-processed data. Also, when the wireless terminal is a PDA terminal, the additional peripheral device 250 may include all applications except for a communication function.
As described above, the coprocessor 200 represents a processor capable of executing functions or application programs requiring high speed in the system, such as a graphic user interface (GUI), a multimedia codec, and so on. Further, the main processor 100 represents a processor controlling the general operation of the system. For instance, in the case of a wireless terminal, the main processor 100 may become a modem chip such as an Mobile Station Modem (MSM). Each of the boot modules stored in the first flash memories 110 and 210 represents a software module which initializes an operation of a corresponding processor and can actually shift into a main software routine. Further, the loader module represents a software module for moving the remaining main software code portions to a memory area which can be controlled by a controller, when only some necessary modules other than the remaining main software code portions are initialized and operated after booting. The bootloader module represents a software module in which the boot module is combined with the loader module. The flash file system represents a software module which enables data to be stored in the flash memory without an error or be read from the flash memory without an error.
In FIG. 1, the first flash memories 110 and 210 may become NOR-type flash memories and the second flash memories 120 and 220 may become NAND-type flash memories. Herein, the NOR flash memory has a stable structure, but it is expensive. Further, the NOR flash memory stores a boot and loader program, and flash file systems. The NAND flash memory is lower priced than the NOR flash memory and can have a high capacity, but it has a greater probability of having a bad sector occurring in the memory. Further, the NAND flash memory mainly stores contents data of a corresponding device. If the NAND flash memory stores the boot and loader program, and the flash file systems, when the bad sector occurs in an area in which the program is stored, an operation of the system cannot be performed. Accordingly, the NOR-type flash memory is generally used as a memory for storing a program and the NAND-type flash memory is generally used as a memory for storing data (such as, contents data, font data, bit map data, phonebook data, and image data), which must not be erased.
As described above, the main processor 100 and the coprocessor 200 each have memories, each of which includes a NOR flash memory, a NAND flash memory, and a RAM. Accordingly, since the main processor 100 and the coprocessor 200 must have such memories respectively, a package space for hardware increases and the cost of the product increases. That is, as shown in FIG. 1, the main processor 100 and the coprocessor 200 each have structures in which the first flash memories, the second flash memories, and the RAMs are independently contained. Since the main processor 100 and the coprocessor 200 must include many memories respectively, many problems occur in achieving miniaturization, low power, and low cost of the terminal.
Accordingly, when the main processor 100 and the coprocessor 200 share the first flash memories, the second flash memories, and the RAMs and the main processor 100 and the coprocessor 200 respectively and independently access the memories when necessary, the number of the memories can be reduced by half.